MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 63

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Intended Audience
Part I is intended for system designers who need a general understanding of the
functionality supported by the MCF5407. It also describes the operation of the MCF5407
ColdFire core and its multiply/accumulate (MAC) execution unit. It describes the
programming and exception models, Harvard memory implementation, and debug module.
Contents
• Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the
• Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the MCF5407
• Chapter 4, “Local Memory.” This chapter describes the MCF5407 implementation
MCF5407. The chapter begins with a description of enhancements from the V3
ColdFire core, and then fully describes the V4 programming model as it is
implemented on the MCF5407. It also includes a full description of exception
handling, data formats, an instruction set summary, and a table of instruction
timings.
multiply/accumulate unit, which executes integer multiply, multiply-accumulate,
and miscellaneous register instructions. The MAC is integrated into the operand
execution pipeline (OEP).
of the ColdFire V4 local memory specification. It consists of the two following
major sections.
— Section 4.2, “SRAM Overview,” describes the MCF5407 on-chip static RAM
— Section 4.7, “Cache Overview,” describes the MCF5407 cache implementation,
(SRAM) implementation. It covers general operations, configuration, and
initialization. It also provides information and examples showing how to
minimize power consumption when using the SRAM.
including organization, configuration, and coherency. It describes cache
operations and how the cache interacts with other memory structures.
Part I. MCF5407 Processor Core
MCF5407 Processor Core
Part I
I-xix