MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 242

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming Model
the resulting SCL bus signal low period is stretched.
8.5 Programming Model
Table 8-1 lists the configuration registers used in the I
8.5.1 I
The IADR holds the address the I
not the address sent on the bus during the address transfer.
Table 8-2 describes IADR fields.
8.5.2 I
The IFDR, Figure 8-6, provides a programmable prescaler to configure the clock for
8-6
7–1
0
Offset
0x28C
MBAR
Bits
0x280
0x284
0x288
0x290
ADR
—
Name
I
I
I
I
I
2
2
2
2
2
Address
2
2
C address register (IADR) [p. 8-6]
C frequency divider register (IFDR) [p. 8-6]
C control register (I2CR) [p. 8-7]
C status register (I2SR) [p. 8-8]
C data I/O register (I2DR) [p. 8-9]
C Address Register (IADR)
C Frequency Divider Register (IFDR)
Reset
Field
R/W
External masters cannot access the MCF5407’s on-chip
memories or MBAR, but can access any I
Slave address. Contains the specific slave address to be used by the I
the default I
Reserved, should be cleared.
Table 8-2. I
7
[31:24]
Figure 8-5. I
2
Table 8-1. I
C mode for an address match on the bus.
6
2
C Address Register Field Descriptions
2
MCF5407 User’s Manual
C responds to when addressed as a slave. Note that it is
2
2
5
C Address Register (IADR)
C Interface Memory Map
NOTE:
ADR
MBAR + 0x280
0000_0000
Read/Write
4
Description
[23:16]
2
3
C interface.
2
C module register.
2
Reserved
Reserved
Reserved
Reserved
Reserved
[15:8]
2
1
C module. Slave mode is
—
0
[7:0]