MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 235

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

possible versions of CLKIN/BCLKO. This figure does not show the skew between CLKIN
and PCLK, PSTCLK, and BCLKO. PSTCLK is half the frequency of PCLK. Similarly, the
skew between PCLK and BCLKO is unspecified.
7.4.2 RSTI Timing
Figure 7-4 shows PLL timing during reset. As shown, RSTI must be asserted for at least 16
CLKIN cycles to give the MCF5407 time to begin its initialization sequence. At this time,
the configuration pins should be asserted (D[2:0] for DIVIDE[2:0]), meeting the minimum
setup and hold times to RSTI given in Chapter 20, “Electrical Specifications.”
On the rising edge of CLKIN before the rising edge of RSTI, the data on D[7:0] is latched
and the PLL begins ramping to its final operating frequency. During this ramp and lock
time, BCLKO and PSTCLK are held low. The PLL locks in about 2 mS or less depending
on the CLKIN frequency, at which time BCLKO begins normal operation in the specified
mode. The PLL requires 50,000 CLKIN cycles to guarantee PLL lock. To allow for reset
of external peripherals requiring a clock source, RSTO remains asserted for a number of
CLKIN cycles, as shown in Figure 7-4. PSTCLK will begin oscillating a minimum of10
clock cycles after RSTO is negated.
CLKIN/BCLKO (/3)
CLKIN/BCLKO (/4)
CLKIN/BCLKO (/5)
CLKIN/BCLKO (/6)
PSTCLK
NOTE:
PCLK
Figure 7-3. CLKIN, PCLK, PSTCLK, and BCLKO Timing
The clock signals are shown with edges aligned to show frequency relationships only.
Actual signal edges have some skew between them.
Chapter 7. Phase-Locked Loop (PLL)
Timing Relationships
7-5