AT90PWM1-16SU Atmel, AT90PWM1-16SU Datasheet - Page 140

• Manufacturer Part Number: AT90PWM1-16SU
• Description: MCU AVR 8K FLASH 16MHZ 24-SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM1-16SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 24-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.8.4
16.8.4.1
16.8.4.2
140
AT90PWM1
PSC Input Configuration
Filter Enable
Signal Polarity
Figure 16-19. Burst Generation
The PSC Input Configuration is done by programming bits in configuration registers.
If the “Filter Enable” bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal.
The disable of this function is mainly needed for prescaled PSC clock sources, where the noise
cancellation gives too high latency.
Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSC clock
to deactivate the outputs (emergency protection of external component). Likewise when used as
fault input, PSCn Input A or Input B have to go through PSC to act on PSCOUTn0/1/2/3 output.
This way needs that CLK
(PAOCnA/B), PSCnIN0/1 input can desactivate directly the PSC output. Notice that in this case,
input is still taken into account as usually by Input Module System as soon as CLK
PSC Input Filterring
One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit
description in Section “PSC n Input A Control Register – PFRCnA”, page 16116.25.13.
PSCOUTn0
PSCOUTn1
PSCn Input A
(high level)
PSCn Input A
(low level)
PSC Input
Module X
CLK
PSC
PSC
OFF
is running. So thanks to PSC Asynchronous Output Control bit
Digital
Filter
4 x CLK
PSC
BURST
Ouput
Stage
PSCn Input A or B
PSCOUTnX
PIN
PSC
4378C–AVR–09/08
is running.