AT90PWM1-16SU Atmel, AT90PWM1-16SU Datasheet - Page 34

• Manufacturer Part Number: AT90PWM1-16SU
• Description: MCU AVR 8K FLASH 16MHZ 24-SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM1-16SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 24-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.7
7.8
34
128 kHz Internal Oscillator
External Clock
AT90PWM1
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is
started as PLL reference clock. If PLL is selected as a system clock source the value for this bit
is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable
CLK
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator.
To drive the device from an external clock source, XTAL1 should be driven as shown in
7-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 7-4.
Table 7-9.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table
Table 7-10.
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
CKSEL3..0
0000
SUT1..0
PLL
00
01
10
11
7-10.
for PSC. After the PLL is enabled, it takes about 100 ms for the PLL to lock.
Start-up Time from Power-
External Clock Drive Configuration
External Clock Frequency
Start-up Times for the External Clock Selection
down and Power-save
6 CK
6 CK
6 CK
External
Signal
Clock
0 - 16 MHz
Frequency Range
NC
Additional Delay from
Reset (V
Reserved
14CK + 4.1 ms
14CK + 65 ms
14CK
CC
= 5.0V)
XTAL2
XTAL1
GND
BOD enabled
Fast rising power
Slowly rising power
Recommended Usage
4378C–AVR–09/08
Figure