S9S08DZ96F2MLF Freescale Semiconductor, S9S08DZ96F2MLF Datasheet - Page 105

• Manufacturer Part Number: S9S08DZ96F2MLF
• Description: MCU 96K FLASH MASK AUTO 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08DZ96F2MLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: S08D
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 6 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 87
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
6.5.1
Port A is controlled by the registers listed below.
6.5.1.1
6.5.1.2
Freescale Semiconductor
PTADD[7:0]
PTAD[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
W
W
R
R
PTADD7
PTAD7
Port A Registers
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Port A Data Register (PTAD)
0
Port A Data Direction Register (PTADD)
0
7
7
PTADD6
PTAD6
0
0
6
6
Figure 6-4. Port A Data Direction Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
Table 6-1. PTAD Register Field Descriptions
Figure 6-3. Port A Data Register (PTAD)
MC9S08DZ128 Series Data Sheet, Rev. 1
PTADD5
PTAD5
0
0
5
5
PTADD4
PTAD4
0
0
4
4
Description
Description
PTADD3
PTAD3
3
0
3
0
PTADD2
PTAD2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTADD1
PTAD1
0
0
1
1
PTADD0
PTAD0
0
0
0
0
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