S9S08DZ96F2MLF Freescale Semiconductor, S9S08DZ96F2MLF Datasheet - Page 120
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S9S08DZ96F2MLF
Manufacturer Part Number
S9S08DZ96F2MLF
Description
MCU 96K FLASH MASK AUTO 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08DV96CLF.pdf
(458 pages)
Specifications of S9S08DZ96F2MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08D
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
6 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
87
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S08DZ96F2MLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 6 Parallel Input/Output Control
6.5.5
Port E is controlled by the registers listed below.
6.5.5.1
6.5.5.2
120
PTEDD[7:0]
PTED[7:0]
Reset:
Reads of this bit always return the pin value of the associated pin, regardless of the value stored in the port data direction bit.
Reset:
PTEDD1 has no effect on the input-only PTE1 pin.
Field
Field
7:0
7:0
W
W
R
R
PTEDD7
PTED7
Port E Registers
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
Port E Data Register (PTED)
0
Port E Data Direction Register (PTEDD)
0
7
7
PTEDD6
PTED6
0
0
6
6
Figure 6-33. Port E Data Direction Register (PTEDD)
Table 6-31. PTEDD Register Field Descriptions
Table 6-30. PTED Register Field Descriptions
Figure 6-32. Port E Data Register (PTED)
MC9S08DZ128 Series Data Sheet, Rev. 1
PTEDD5
PTED5
0
0
5
5
PTEDD4
PTED4
0
0
4
4
Description
Description
PTEDD3
PTED3
3
0
3
0
PTEDD2
PTED2
0
0
2
2
PTEDD1
PTED1
Freescale Semiconductor
0
0
1
1
1
1
PTEDD0
PTED0
0
0
0
0
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