S9S08DZ96F2MLF Freescale Semiconductor, S9S08DZ96F2MLF Datasheet - Page 242
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S9S08DZ96F2MLF
Manufacturer Part Number
S9S08DZ96F2MLF
Description
MCU 96K FLASH MASK AUTO 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08DV96CLF.pdf
(458 pages)
Specifications of S9S08DZ96F2MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08D
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
6 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
87
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S08DZ96F2MLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 11 Inter-Integrated Circuit (S08IICV2)
11.3.5
In slave mode, the same functions are available after an address match has occurred.
The TX bit in IICxC must correctly reflect the desired direction of transfer in master and slave modes for
the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is
desired, reading the IICxD does not initiate the receive.
Reading the IICxD returns the last byte received while the IIC is configured in master receive or slave
receive modes. The IICxD does not reflect every byte transmitted on the IIC bus, nor can software verify
that a byte has been written to the IICxD correctly by reading it back.
In master transmit mode, the first byte of data written to IICxD following assertion of MST is used for the
address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required
R/W bit (in position bit 0).
11.3.6
242
Reset
Reset
Field
DATA
7–0
W
W
R
R
GCAEN
IIC Data I/O Register (IICxD)
IIC Control Register 2 (IICxC2)
Data — In master transmit mode, when data is written to the IICxD, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
0
0
7
7
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IICxD register to prevent an inadvertent
initiation of a master receive data transfer.
= Unimplemented or Reserved
ADEXT
0
0
6
6
Figure 11-8. IIC Control Register (IICxC2)
Figure 11-7. IIC Data I/O Register (IICxD)
MC9S08DZ128 Series Data Sheet, Rev. 1
Table 11-8. IICxD Field Descriptions
0
0
0
5
5
NOTE
0
0
0
4
4
Description
DATA
3
0
3
0
0
AD10
0
0
2
2
Freescale Semiconductor
AD9
0
0
1
1
AD8
0
0
0
0
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