S9S08DZ96F2MLF Freescale Semiconductor, S9S08DZ96F2MLF Datasheet - Page 189

• Manufacturer Part Number: S9S08DZ96F2MLF
• Description: MCU 96K FLASH MASK AUTO 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08DZ96F2MLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: S08D
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 6 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 87
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
3. Lastly, PBE mode transitions into PEE mode:
a) BLPE: If a transition through BLPE mode is desired, first set LP (bit 3) in MCGC2 to 1.
b) BLPE/PBE: MCGC3 = 0x58 (%01011000)
c) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to
d) PBE: Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the
e) PBE: Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock
a) MCGC1 = 0x18 (%00011000)
b) Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is selected
– PLLS (bit 6) set to 1, selects the PLL. At this time, with an RDIV value of %011, the FLL
– DIV32 (bit 4) still set at 1. Because the MCG is in a PLL mode, the DIV32 bit is ignored.
– VDIV (bits 3-0) set to %1000, or multiply-by-32 because 1 MHz reference * 32= 32MHz.
PBE mode
PLLS clock is the PLL
– CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the
to feed MCGOUT in the current clock mode
– Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-32,
reference divider of 256 is switched to the PLL reference divider of 8 (see
resulting in a reference frequency of 8 MHz/ 8 = 1 MHz. In BLPE mode,changing the PLLS
bit only prepares the MCG for PLL usage in PBE mode
Keeping it set at 1 makes transitions back into an FLL external mode easier.
In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is
disabled. Changing them only sets up the multiply value for PLL usage in PBE mode
system clock source
MCGOUT = [(8 MHz / 8) * 32] / 1 = 32 MHz, and the bus frequency is MCGOUT / 2, or
16 MHz
MC9S08DZ128 Series Data Sheet, Rev. 1
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
Table
8-3),
189