S9S08DZ96F2MLF Freescale Semiconductor, S9S08DZ96F2MLF Datasheet - Page 194

• Manufacturer Part Number: S9S08DZ96F2MLF
• Description: MCU 96K FLASH MASK AUTO 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08DZ96F2MLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: S08D
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 6 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 87
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
8.5.3.3
In this example, the MCG will move through the proper operational modes from BLPI mode at a 16 kHz
bus frequency running off of the internal reference clock (see previous example) to FEE mode using an
8MHz crystal configured for a 16 MHz bus frequency. First, the code sequence will be described. Then a
flowchart will be included which illustrates the sequence.
194
1. First, BLPI must transition to FBI mode.
2. Next, FBI will transition to FEE mode.
a) MCGC2 = 0x00 (%00000000)
b) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has acquired
a) MCGC2 = 0x36 (%00110110)
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
c) MCGC1 = 0x18 (%00011000)
d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference clock is the current
e) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has
f) Loop until CLKST (bits 3 and 2) in MCGSC are %00, indicating that the output of the FLL is
g) Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 1024, and a bus divider
h) At this point, by default, DRS (bit 0) in MCGT is set to 1 and DMX32 (bit 5) in MCGT is
– LP (bit 3) in MCGSC is 0
lock. Although the FLL is bypassed in FBI mode, it is still enabled and running.
– RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure external oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
has been initialized.
– CLKS (bits 7 and 6) set to %00 in order to select the output of the FLL as system clock
– RDIV (bits 5-3) remain at %011, or divide-by-256 for a reference of 8 MHz / 256 = 31.25
– IREFS (bit 1) cleared to 0, selecting the external reference clock
source for the reference clock
reacquired lock.
selected to feed MCGOUT
of 1, MCGOUT = 31.25 kHz * 1024 / 1 = 32 MHz. Therefore, the bus frequency is 16 MHz.
cleared to 0. If a bus frequency of 8 MHz is desired instead, clear DRS to 0 to switch the FLL
multiplication factor from 1024 to 512 and loop until LOCK (bit 6) in MCGSC is set, indicating
that the FLL has reacquired LOCK. To return the bus frequency to 16 MHz, set DRS to 1 again,
and the FLL multiplication factor will switch back to 1024. Then loop again until the LOCK
bit is set.
Example #3: Moving from BLPI to FEE Mode: External Crystal = 8 MHz,
Bus Frequency = 16 MHz
source
kHz.
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor