S9S08DZ96F2MLF Freescale Semiconductor, S9S08DZ96F2MLF Datasheet - Page 405

• Manufacturer Part Number: S9S08DZ96F2MLF
• Description: MCU 96K FLASH MASK AUTO 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08DZ96F2MLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: S08D
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 6 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 87
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.3.12 Debug FIFO Extended Information Register (DBGFX)
1
Freescale Semiconductor
end-run
Module Base + 0x000B
end-run
or non-
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
PPACC
Reset
Bit 16
Field
POR
7
0
W
R
1
PPACC
PPAGE Access Indicator Bit — This bit indicates whether the captured information in the current FIFO word is
associated with an extended access through the PPAGE mechanism or not. This is indicated by the internal
signal mmu_ppage_sel which is 1 when the access is through the PPAGE mechanism.
0 The information in the corresponding FIFO word is event-only data or an unpaged 17-bit CPU address with
1 The information in the corresponding FIFO word is a 17-bit flash address with PPAGE[2:0] in the three most
Extended Address Bit 16 — This bit is the most significant bit of the 17-bit core address.
U
0
7
bit-16 = 0
significant bits and CPU address[13:0] in the 14 least significant bits
Figure 18-13. Debug FIFO Extended Information Register (DBGFX)
= Unimplemented or Reserved
0
0
0
6
Table 18-14. DBGFX Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
0
0
0
5
0
0
0
4
Description
0
0
0
3
Chapter 18 Debug Module (S08DBGV3) (128K)
0
0
0
2
0
0
0
1
Bit 16
U
0
0
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