M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 139

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
2.03
2.04
REVISION HISTORY
Aug 31, 2006
Feb 02, 2007
Date
64 to 66
13, 60
43, 44
Page
75
76
14
15
16
23
25
31
34
35
36
41
43
46
51
52
53
54
59
61
71
72
73
75
78
80
Table 16: Max. of f( φ ) : 2 × V
Table 17: Test condition of V
Table 24
Limits of t
MEMORY
ROM: Description revised.
ROM Code Protect Address: Description revised and added.
Fig. 10: Reserved ROM area: FFD0
Fig.8 and Fig.60: CPUM2 (bits 2 to 7) revised.
• Direction Resisters: Description revised.
Fig.11: ROM correction enable register →
Table 8: Terminations 1 and 2 of V
• Fig.13: PULL3 (bits 4 to 7), SEG2 (bits 4 to 7) revised.
Fig.19: INTEDGE(bit 6), ICON2(bit 7) revised.
Fig.25: revised.
Fig. 28: Note added and revised.
Fig. 27: TXCON(BITS 3,4) revised.
Fig. 36: Note added.
• Fig.29: TYM(bits 2,3) revised.
• [AD control Register], Fig.39:
Fig. 38: Note added.
analog input selection bit → analog input pin selection bits
Fig. 45: 1/3 duty revised.
ROM CORRECTION FUNCTION: Description added.
Fig. 47: FFD0
Fig. 49: Note added and revised.
Fig.40: LM2(bits 1 to 7) revised.
Fig.51: CKOUT(bits 2 to 7 ) revised.
Fig. 59: Note 3 added and circuit expression is revised.
Table 12: ESDA input → ESDA input/output
Fig. 63 to Fig. 66: Revised.
Precautions Regarding Overvoltage: Description revised and Fig. 73 added.
Table 13
• V
• V
• V
Table 14
• V
• Note 3 revised.
Table 16: Note 4 revised.
Table 20
• T
• Note 2 revised.
Note: ...set f(X
Table 22
tsu (R
o
CONV
CC
I
IL
: OSCSEL added.
: Conditions added.
: OSCSEL added.
: Oscillation start voltage → When start oscillating
X
D-S
ROM correction enable register(RCR)
Limits: (Note) → (Notes 1, 2)
wH
V on RESET
CLK2
(S
16
IN
CLK2
) → t
) ≤ 500 kHz → ≥ 500 kHz
→ FFDB
), t
su
(3/7)
wL
(S
(S
IN2
16
38D5 Group Data Sheet
CLK2
.
-S
CC
T+
Description
CLK2
– V
– 4 → 4
): t
T-
c
L3
)
(S
16
: V
Summary
revised.
CLK1
→ FFDB
CC
= 2.0 V on RESET → V
)/2–80 → t
16
c
(S
CLK2
)/2–80
CC
= 2.0 V to 5.5