M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 21

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
Fig. 11 Memory map of special function register (SFR)
Note 1: The blanks are reserved. Do not write data to these areas.
0FE0
0FE1
0FE2
0FE3
0FE4
0FE5
0FE6
0FE7
0FE8
0FE9
0FEA
0FEB
0FEC
0FED
0FEE
0FEF
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
001A
001B
001C
001D
001E
001F
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2: No memory access is allowed to the blank areas within the SFRs.
3: Addresses 0FE0
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
CPU mode register 2 (CPUM2)
RRF register (RRFR)
LCD mode register1 (LM1)
LCD mode register2 (LM2)
AD control register (ADCON)
AD conversion register (low-order) (ADL)
AD conversion register (high-order) (ADH)
Transmit/receive buffer register 1 (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Serial I/O2 control register (SIO2CON)
Reserved
Serial I/O2 register (SIO2)
Flash memory control register 0 (FMCR0)
Flash memory control register 1 (FMCR1)
Flash memory control register 2 (FMCR2)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
May 20, 2008 Page 19 of 134
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
16
to 0FEF
16
are available in the flash memory version only.
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
002B
002C
002D
002E
002F
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
003A
003B
003C
003D
003E
003F
0FF0
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Timer X (low-order) (TXL)
Timer X (high-order) (TXH)
Timer X (extension) (TXEX)
Timer X mode register (TXM)
Timer X control register 1 (TXCON1)
Timer X control register 2 (TXCON2)
Compare register 1 (low-order) (COMP1L)
Compare register 1 (high-order) (COMP1H)
Compare register 2 (low-order) (COMP2L)
Compare register 2 (high-order) (COMP2H)
Compare register 3 (low-order) (COMP3L)
Compare register 3 (high-order) (COMP3H)
Timer Y (low-order) (TYL)
Timer Y (high-order) (TYH)
Timer Y mode register (TYM)
Timer Y control register (TYCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
PWM01 register (PWM01)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Timer 1234 mode register (T1234M)
Timer 1234 frequency division selection register (PRE1234)
Watchdog timer control register (WDTCON)
PULL register 1 (PULL1)
PULL register 2 (PULL2)
PULL register 3 (PULL3)
Clock output control register (CKOUT)
Segment output disable register 0 (SEG0)
Segment output disable register 1 (SEG1)
Segment output disable register 2 (SEG2)
Key input control register (KIC)
ROM correction address 1 high-order register (RCA1H)
ROM correction address 1 low-order register (RCA1L)
ROM correction address 2 high-order register (RCA2H)
ROM correction address 2 low-order register (RCA2L)
ROM correction enable register (RCR)
Reserved
Reserved
Reserved
(1)
(1)
(1)