M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 141

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
3.01
REVISION HISTORY
Aug 08, 2007
Date
73 to 91
69, 70
Page
37
38
39
40
41
42
47
48
49
50
51
53
56
57
58
59
60
61
62
64
65
66
92
93
94
Fig. 28: Timer X output 2 edge switch bit → Timer X output 2 active edge switch bit
• Frequency Divided For Timer: revised
timer X1 output edge switch bit → timer X output 1 active edge switch bit
timer X2 output edge switch bit → timer X output 2 active edge switch bit
(6) Pulse Width Measurement Mode: revised
(1) Write Order to Timer X: description added
(2) Read Order to Timer X: revised
(3) Write to Timer X: revised
(7) When Timer X Pulse Width Measurement Mode Used: added
Fig. 30: Timer X output 1 edge switch bit → Timer X output 1 active edge switch bit
• Timer Y: revised
(5) Real Time Port Control: moved from <Notes on Timer Y>
• Real Time Port Control: moved to “ • Timer Y”
• Serial I/O2: revised
Fig. 39: Serial I/O counter 2 → Serial I/O2 counter
Serial I/O shift register 2 → Serial I/O2 register
[Serial I/O2 Operation]: added
Fig. 40: revised
[Comparator and Control Circuit]: revised
ADKEY function: moved from the next page.
Fig. 43: Added the note number to each register
• Voltage Multiplier: revised
• Bias Control and Applied Voltage to LCD Power Input Pins: evised
Fig. 45: revised
<Notes>: added
Fig. 50: revised
• Initial Value of Watchdog Timer: revised
<Notes>: revised
Fig. 52: Watchdog timer selection bit 2 → Watchdog timer count source selection bit
Fig. 53: revised
Title “[RRF register] RRFR”: added
RESET CIRCUIT: description added
Fig. 57, Fig. 58: revised
Fig. 59: (18) RRF register (RRFR) → (18) RRF register
CLOCK GENERATING CIRCUIT, and • Frequency Control: Description added
• Oscillation Control: Description added
Fig. 63: revised
Table 15: Function of V
Fig. 66 and 67: revised
FLASH MEMORY MODE: added
NOTES ON PROGRAMMING is merged to NOTES ON USE
NOTES ON QzROM VERSION is separated
NOTES ON FLASH MEMORY VERSION and NOTES ON DEFFAERENCES
BETWEEN QzROM VERSION AND FLASH MEMORY VERSION are added
2
Do not write “1” → Not used (do not write “1”)
title is revised
Notes revised
(5/7)
CC
, V
38D5 Group Data Sheet
SS
Description
pins: 1.8 to 5.5 → 2.7 to 5.5
Summary