DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 172
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 172 of 843
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Section 6 Bus Controller
16-Bit Access Areas: Figure 6.7 illustrates data alignment control for 16-bit access areas. With
16-bit access areas, the upper data bus (D
accesses. The amount of data that can be accessed at one time is one byte or one word, and a
longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
6.4.3
Table 6.4 shows the data buses used, and the valid strobes, for the access spaces.
In a read, the
In a write, the
lower half.
Rev. 2.00 Sep 20, 2005 page 132 of 800
REJ09B0260-0200
Byte size
Byte size
Word size
Longword size
Figure 6.7 Access Sizes and Data Alignment Control (16-Bit Access Area)
Valid Strobes
R D
H W R
signal is valid for both the upper and the lower half of the data bus.
signal is valid for the upper half of the data bus, and the
• Even address
• Odd address
1st bus cycle
2nd bus cycle
15
to D
8
D
) and lower data bus (D
15
Upper data bus
D
8
D
7
7
Lower data bus
to D
L W R
0
) are used for
signal for the
D
0
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