DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 228
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 I/O Ports
Rev. 2.00 Sep 20, 2005 page 188 of 800
REJ09B0260-0200
Port A
Figure 7.10 Port A Pin Configuration
Port A pins
PA /TP /TIOCB /A
PA /TP /TIOCA /A
PA /TP /TIOCB /A
PA /TP /TIOCA /A
PA /TP /TIOCB /TCLKD
PA /TP /TIOCA /TCLKC
PA /TP /TCLKB
PA /TP /TCLKA
Pin functions in modes 1, 2, 6 and 7
PA (input/output)/TP (output)/TIOCB (input/output)
PA (input/output)/TP (output)/TIOCA (input/output)
PA (input/output)/TP (output)/TIOCB (input/output)
PA (input/output)/TP (output)/TIOCA (input/output)
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TCLKB (input)
PA (input/output)/TP (output)/TCLKA (input)
Pin functions in modes 3 and 4
PA (input/output)/TP (output)/TIOCA (input/output)/A
PA (input/output)/TP (output)/TIOCB (input/output)/A
PA (input/output)/TP (output)/TIOCA (input/output)/A
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TCLKB (input)
PA (input/output)/TP (output)/TCLKA (input)
Pin functions in mode 5
PA
PA
PA
PA
PA
PA
PA
PA
A
20
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
(output)
(input/output)/TP
(input/output)/TP
(input/output)/TP
(input/output)/TP
(input/output)/TP
(input/output)/TP
(input/output)/TP
(input/output)/TP
7
6
5
4
3
2
1
0
2
2
1
1
0
0
20
21
23
22
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
(output)/TIOCB
(output)/TIOCA
(output)/TIOCB
(output)/TIOCA
(output)/TIOCB
(output)/TIOCA
(output)/TCLKB (input)
(output)/TCLKA (input)
2
2
1
1
0
0
2
2
1
1
0
0
2
1
1
0
0
(input/output)/A
(input/output)/A
(input/output)/A
(input/output)/A
(input/output)/TCLKD (input)
(input/output)/TCLKC (input)
20
21
22
23
21
22
23
(output)
(output)
(output)
(output)
(output)
(output)
(output)
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