DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 92
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 2 CPU
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.
Figure 2.14 shows the stack after the exception-handling sequence.
2.8.5
In this state the bus is released to a bus master other than the CPU, in response to a bus request.
The bus masters other than the CPU is an external bus master. While the bus is released, the CPU
halts except for internal operations. Interrupt requests are not accepted. For details see section 6.6,
Bus Arbiter.
Rev. 2.00 Sep 20, 2005 page 52 of 800
REJ09B0260-0200
SP (ER7)
Legend:
CCR:
SP:
Notes: 1.
SP–4
SP–3
SP–2
SP–1
Condition code register
Stack pointer
2.
Bus-Released State
PC is the address of the first instruction executed after the return from the
exception-handling routine.
Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2.14 Stack Structure after Exception Handling
Before exception
handling starts
Stack area
Pushed on stack
SP (ER7)
SP+1
SP+2
SP+3
SP+4
After exception
handling ends
CCR
PC
Even
address
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