DF2378RVFQ34WV Renesas Electronics America, DF2378RVFQ34WV Datasheet - Page 371

• Manufacturer Part Number: DF2378RVFQ34WV
• Description: MCU 3V 512K I-TEMP PB-FREE 144-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
2
1
0
Bit Name
DTIE1A
DTIE0B
DTIE0A
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Data Transfer End Interrupt Enable 1A
Enables or disables an interrupt to the CPU or DTC
when transfer ends. If the DTE1 bit is cleared to 1
when DTIE1A = 1, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE1A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE1 bit to 1.
Data Transfer Interrupt Enable 0B
Enables or disables an interrupt to the CPU or DTC
when transfer on channel 1 is interrupted. If the
DTME0 bit is cleared to 0 when DTIE0B = 1, the
DMAC regards this as indicating a break in the
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either by
clearing the DTIE0B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME0 bit to 1.
Data Transfer End Interrupt Enable 0A
Enables or disables an interrupt to the CPU or DTC
when transfer ends. If the DTE0 bit is cleared to 0
when DTIE0A = 1, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE0A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE0 bit to 1.
Rev.7.00 Mar. 18, 2009 page 303 of 1136
Section 7 DMA Controller (DMAC)
REJ09B0109-0700