DF2378RVFQ34WV Renesas Electronics America, DF2378RVFQ34WV Datasheet - Page 490

• Manufacturer Part Number: DF2378RVFQ34WV
• Description: MCU 3V 512K I-TEMP PB-FREE 144-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 EXDMA Controller (EXDMAC)
8.6
8.6.1
Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in
operation (including the transfer standby state). Transfer must be disabled before changing a
setting for an operational channel.
8.6.2
When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC
enters the module stop state. However, 1 cannot be written to the MSTP14 bit when any of the
EXDMAC’s channels is enabled for transfer, or when an interrupt is being requested. Before
setting the MSTP14 bit, first clear the EDA bit in EDMDR to 0, then clear the IRF or EDIE bit in
EDMDR to 0.
When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following
EXDMAC register settings remain valid in the module stop state, and so should be changed, if
necessary, before making the module stop transition.
• ETENDE = 1 in EDMDR (ETEND pin enable)
• EDRAKE = 1 in EDMDR (EDRAK pin enable)
• AMS = 1 in EDMDR (EDACK pin enable)
8.6.3
Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC internal
operations, as indicated below.
[1] Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to [2].
[2] Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3].
[3] Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to [1].
After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used
for the initial activation after transfer is enabled.
Rev.7.00 Mar. 18, 2009 page 422 of 1136
REJ09B0109-0700
Usage Notes
EXDMAC Register Access during Operation
Module Stop State
EDREQ Pin Falling Edge Activation