DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 151

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 5.6
Legend:
O :
X:
IM:
PR:
⎯:
Notes: 1. Set to 1 when an interrupt is accepted.
5.5.2
Enabling and disabling of IRQ interrupts and on-chip peripheral module interrupts can be set by
means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and
disabled when set to 1.
Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. The I bit is referred to. If the I bit is cleared to 0, an interrupt request is accepted. If the I bit is
3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
Interrupt
Control
Mode
0
2
interrupt request is sent to the interrupt controller.
set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending.
the priority system is accepted, and other interrupt requests are held pending.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
No operation. (All interrupts enabled)
Not used
Interrupt operation control performed
Used as interrupt mask bit
Sets priority
2. Keep the initial setting.
Interrupt Control Mode 0
Setting
INTM
1
0
1
Operations and Control Signal Functions in Each Interrupt Control Mode
INTM
0
0
0
Interrupt
Acceptance
Control
O
X
I
IM
⎯*
1
8-Level Control
X
O
I2 to
I0
⎯
IM
Rev. 6.00 Sep. 24, 2009 Page 103 of 928
IPR
⎯*
PR
2
Default Priority
Determination T (Trace)
O
O
Section 5 Interrupt Controller
REJ09B0099-0600
⎯
T