DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 634

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
17.3.23 IEBus Receive Error Flag Register (IEREF)
IEREF checks the source of an RxE interrupt indicated in IERSR. This register detects an overrun
error, timing error, overflow of a maximum number of bytes in one frame, and parity error.
These flags become valid when the receive start flag (RxS) is set to 1. If an error occurs before the
RxS flag is set to 1, the IEB terminates the communications and enters the wait state. In this case,
these flags will not be set and the RxE flag is not set.
Rev. 6.00 Sep. 24, 2009 Page 586 of 928
REJ09B0099-0600
Bit
7 to 4 ⎯
3
Bit Name
OVE
Initial
Value
All 0
0
R/W
⎯
R/W
Description
Reserved
These bits are always read as 0 and cannot be modified.
Overrun Control Flag
Used to control the overrun during data reception. The IEB
sets the OVE and RxE flags when the IEB receives the
next byte data while the receive data has not been read
(the RxRDY flag is not cleared) and when the parity bit
reception has been started. If this flag remains set until
acknowledge bit transfer, the IEB assumes that an
overrun error has occurred and returns a NAK to the
communications destination unit.
The communications destination unit retransmits data up
to the maximum number of transmit bytes. The IEB,
however, returns a NAK when this flag remains set
because the IEB assumes that the overrun error has not
been cleared.
If this flag is cleared to 0, the IEB decides that the overrun
error has been cleared, returns an ACK, and receives the
next data.
In broadcast reception, if this flag is set during
acknowledge bit transmission, the IEB immediately enters
the wait state.
[Setting condition]
•
[Clearing condition]
•
When the next byte data is received while the RxRDY
flag is not cleared and when the parity bit of the data is
received.
When writing 0 after reading OVE = 1