DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 367
DF2505FC26V
Manufacturer Part Number
DF2505FC26V
Description
IC H8S/2505 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2505FC26V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Example of Cascaded Operation Setting Procedure: Figure 10.17 shows an example of the
setting procedure for cascaded operation.
Examples of Cascaded Operation: Figure 10.18 illustrates the operation when TCNT_2
overflow/underflow counting has been set for TCNT_1, when TGRA_1 and TGRA_2 have been
designated as input capture registers, and when TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
Figure 10.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for
TCNT_1 and phase counting mode has been designated for channel 2.
TCNT_1
clock
TCNT_1
TCNT_2
clock
TCNT_2
TIOCA1,
TIOCA2
TGRA_1
TGRA_2
<Cascaded operation>
H'FFFF
H'03A1
Cascaded operation
Figure 10.17 Cascaded Operation Setting Procedure
Set cascading
Start count
Figure 10.18 Example of Cascaded Operation (1)
[1]
[2]
H'0000
[1]
[2]
Set the TPSC2 to TPSC0 bits in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
H'03A2
H'03A2
H'0000
Rev. 6.00 Sep. 24, 2009 Page 319 of 928
Section 10 16-Bit Timer Pulse Unit (TPU)
H'0001
REJ09B0099-0600
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