DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 330

IC H8S/2505 MCU FLASH 144QFP

DF2505FC26V

Manufacturer Part Number
DF2505FC26V
Description
IC H8S/2505 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2505FC26V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.11 MD0 to MD3
Legend:
X:
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
10.3.3
The TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required as TIOR is affected by
the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
Rev. 6.00 Sep. 24, 2009 Page 282 of 928
REJ09B0099-0600
Bit 3
MD3*
0
1
1
Don’t care
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
Timer I/O Control Register (TIOR)
Bit 2
MD2*
0
1
X
be written to MD2.
2
Bit 1
MD1
0
1
0
1
X
Bit 0
MD0
0
1
0
1
0
1
0
1
X
Description
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4

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