DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 209

IC H8S/2505 MCU FLASH 144QFP

DF2505FC26V

Manufacturer Part Number
DF2505FC26V
Description
IC H8S/2505 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2505FC26V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH
is set to 1, an idle cycle is inserted at the start of the write cycle.
Figure 7.28 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
φ
(a) Idle cycle not inserted
(ICIS0 = 0)
T
Bus cycle A
1
Figure 7.28 Example of Idle Cycle Operation (2)
Long output floating time
T
2
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
φ
Rev. 6.00 Sep. 24, 2009 Page 161 of 928
T
1
Bus cycle A
(b) Idle cycle inserted
(Initial value: ICIS0 = 1)
T
2
T
3
Section 7 Bus Controller
T
Bus cycle B
I
T
REJ09B0099-0600
1
T
2

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