DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 551
DF2505FC26V
Manufacturer Part Number
DF2505FC26V
Description
IC H8S/2505 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2505FC26V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is
14.4.7
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 14.16 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
processing
ICDRR
ICDRS
(Input)
RDRF
MST
TRS
SCL
SDA
User
RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and
AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.
fixed high after receiving the next byte data.
Noise Canceler
[2] Set MST
(when outputting the clock)
Bit 0
1
Figure 14.15 Receive Mode Operation Timing
Data 1
Bit 1
2
Bit 6
7
[3] Read ICDRR
Bit 7
8
Bit 0
Data 2
1
Data 1
Rev. 6.00 Sep. 24, 2009 Page 503 of 928
Section 14 I
Bit 6
7
Bit 7
2
C Bus Interface 2 (IIC2)
8
REJ09B0099-0600
Bit 0
1
[3] Read ICDRR
Data 2
Data 3
Bit 1
2
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