DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 479

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 13.7 shows a sample flowchart for data transmission.
and clear TDRE flag in SSR to 0
Write transmit data to TDR
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted?
Clear DR to 0 and
Start transmission
Break output?
set DDR to 1
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Yes
Figure 13.7 Sample Serial Transmission Flowchart
No
No
No
No
[1]
[2]
[3]
[4]
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Serial transmission continuation
[4] Break output at the end of serial
Note: * The case, where the TDRE flag check and clearing are
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DTC* is
activated by a transmit data empty
interrupt (TXI) request, and data is
written to TDR.
transmission:
To output a break in serial
transmission, clear DR for the port
corresponding to the TxD pin to 0,
set DDR to 1, then clear the TE bit
in SCR to 0.
Section 13 Serial Communication Interface (SCI)
automatically executed by DTC,
occurs only when the DISEL bit in DTC is 0
with the transfer counter other than 0.
Therefore, when the DISEL bit is 1, or
both the DISEL bit and the transfer counter are 0,
give the CPU an instruction to clear the TDRE flag.
Rev. 6.00 Sep. 24, 2009 Page 431 of 928
REJ09B0099-0600