UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 14

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) ................................................................... 608
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 631
14
17.7
17.8
17.9
17.10 Error Detection...................................................................................................................... 584
17.11 Extension Code..................................................................................................................... 584
17.12 Arbitration ............................................................................................................................. 585
17.13 Wakeup Function.................................................................................................................. 586
17.14 Communication Reservation............................................................................................... 587
17.15 Cautions ................................................................................................................................ 592
17.16 Communication Operations................................................................................................. 593
17.17 Timing of Data Communication .......................................................................................... 601
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10 DMA Abort Factors............................................................................................................... 621
18.11 End of DMA Transfer............................................................................................................ 621
18.12 Operation Timing .................................................................................................................. 621
18.13 Cautions ................................................................................................................................ 626
19.1
19.2
19.3
I
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 582
Address Match Detection Method ...................................................................................... 584
17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................587
17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1).......................591
17.16.1 Master operation in single master system ................................................................................594
17.16.2 Master operation in multimaster system ...................................................................................595
17.16.3 Slave operation........................................................................................................................598
Features................................................................................................................................. 608
Configuration ........................................................................................................................ 609
Registers ............................................................................................................................... 610
Transfer Targets ................................................................................................................... 617
Transfer Modes ..................................................................................................................... 617
Transfer Types ...................................................................................................................... 618
DMA Channel Priorities........................................................................................................ 619
Time Related to DMA Transfer ............................................................................................ 619
DMA Transfer Start Factors................................................................................................. 620
Features................................................................................................................................. 631
Non-Maskable Interrupts ..................................................................................................... 635
19.2.1
19.2.2
19.2.3
Maskable Interrupts.............................................................................................................. 640
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
2
C Interrupt Request Signals (INTIICn) .............................................................................. 562
Master device operation...........................................................................................................562
Slave device operation (when receiving slave address data (address match))........................565
Slave device operation (when receiving extension code) ........................................................569
Operation without communication............................................................................................573
Arbitration loss operation (operation as slave after arbitration loss).........................................573
Operation when arbitration loss occurs (no communication after arbitration loss) ...................575
Operation .................................................................................................................................637
Restore ....................................................................................................................................638
NP flag .....................................................................................................................................639
Operation .................................................................................................................................640
Restore ....................................................................................................................................642
Priorities of maskable interrupts...............................................................................................643
Interrupt control register (xxICn) ..............................................................................................647
Interrupt mask registers 0 to 3 (IMR0 to IMR3)........................................................................649
Preliminary User’s Manual U18952EJ1V0UD