UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 750

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UPD70F3736GK-GAK-AX

Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3736GK-GAK-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
28.5.4 Flash functions
28.5.5 Pin processing
750
(1) FLMD0 pin
Caution Make sure that the FLMD0 pin is at 0 V when reset is released.
The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from
being written during self rewriting. It is therefore necessary to keep the voltage applied to the FLMD0 pin at 0
V when reset is released and a normal operation is executed. It is also necessary to apply a voltage of V
level to the FLMD0 pin during the self programming mode period via port control before the memory is
rewritten.
When self programming has been completed, the voltage on the FLMD0 pin must be returned to 0 V.
FlashInit
FlashEnv
FlashFLMDCheck
FlashStatusCheck
FlashBlockErase
FlashWordWrite
FlashBlockIVerify
FlashBlockBlankCheck
FlashSetInfo
FlashGetInfo
FlashBootSwap
Function Name
RESET signal
FLMD0 pin
Figure 28-18. Mode Change Timing
Preliminary User’s Manual U18952EJ1V0UD
Table 28-10. Flash Function List
Blank check of block
Self-programming library initialization
Flash environment start/end
FLMD pin check
Hardware processing execution status check
Block erase
Data write
Internal verification of block
Flash information setting
Flash information acquisition
Boot swap execution
CHAPTER 28 FLASH MEMORY
V
V
0 V
0 V
DD
DD
operation mode
Normal
Self programming mode
Outline
operation mode
Normal
Support
DD

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