UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 247

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<1> Count operation start flow
<2> TPnCCR0, TPnCCR1 register
setting change flow
(TPnCKS0 to TPnCKS2 bits)
Setting of TPnCCR0 register
Setting of TPnCCR1 register
Register initial setting
TPnCCR0 register,
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
TPnCCR1 register
TPnCTL0 register
Remark
TPnCE bit = 1
START
n = 0 to 2, 5
m = 0, 1
Figure 7-27. Software Processing Flow in PWM Output Mode (2/2)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Initial setting of these
registers is performed
before setting the
TPnCE bit to 1.
The TPnCKS0 to
TPnCKS2 bits can be
set at the same time
when counting is
enabled (TPnCE bit = 1).
TPnCCR1 write
processing is necessary
only when the set cycle
is changed.
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to the
CCRm buffer register.
Preliminary User’s Manual U18952EJ1V0UD
<3> TPnCCR0, TPnCCR1 register
<4> TPnCCR0, TPnCCR1 register
<5> Count operation stop flow
setting change flow
setting change flow
Setting of TPnCCR1 register
Setting of TPnCCR0 register
Setting of TPnCCR1 register
TPnCE bit = 0
STOP
Counting is stopped.
Only writing of the TPnCCR1
register must be performed
when the set duty factor is
changed. When the counter is
cleared after setting, the
value of compare register m
is transferred to the CCRm
buffer register.
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to the
CCRm buffer register.
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