UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 311
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(b) Notes on rewriting the TQ0CCR0 register
To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the
set value.
If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
If the value of the TQ0CCR0 register is changed from D
less than D
has been rewritten. Consequently, the value that is compared with the 16-bit counter is D
Because the count value has already exceeded D
overflows, and then counts up again from 0000H. When the count value matches D
signal is generated.
Therefore, the INTTQ0CC0 signal may not be generated at the valid edge count of “(D
+ 1) times” originally expected, but may be generated at the valid edge count of “(10000H + D
INTTQ0CC0 signal
TQ0CCR0 register
16-bit counter
1
, the count value is transferred to the CCR0 buffer register as soon as the TQ0CCR0 register
TQ0CE bit
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Preliminary User’s Manual U18952EJ1V0UD
External event
count signal
interval (1)
(D
1
+ 1)
D
1
D
1
External event count signal
interval (NG)
(10000H + D
D
2
2
, however, the 16-bit counter counts up to FFFFH,
D
1
1
to D
2
+ 1)
2
while the count value is greater than D
D
2
D
2
External event
count signal
interval (2)
(D
D
2
+ 1)
2
1
2
, the INTTQ0CC0
+ 1) times” or “(D
2
.
2
+ 1) times”.
2
311
but
2
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