UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 267
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(i) Operation to write 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting)
(e) Clearing overflow flag
(TPnOVF bit)
(TPnOVF bit)
Overflow flag
Overflow flag
0 write signal
0 write signal
The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by
writing 8-bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF
bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Remark
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of
overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no
overflow has occurred even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is
cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear
instruction.
set signal
set signal
Overflow
Overflow
n = 0 to 2, 5
L
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Preliminary User’s Manual U18952EJ1V0UD
(iii) Operation to clear to 0 (without conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
access signal
access signal
(TPnOVF bit)
(TPnOVF bit)
Overflow flag
Overflow flag
0 write signal
0 write signal
set signal
set signal
Overflow
Overflow
Register
Register
L
H
Read
Read
Write
Write
267
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