MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 211

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

15.4.1 Polled LVI Operation
15.4.2 Forced Reset Operation
MC68HC908AS60 — Rev. 1.0
$FE0F
Addr.
LVI Status Register
Register Name
See page 212.
(LVISR)
Once an LVI reset occurs, the MCU remains in reset until V
above a voltage, LVI
CPU cycle to bring the MCU out of reset. See
Operation. The output of the comparator controls the state of the
LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
In applications that can operate at V
software can monitor V
register, the LVIPWR bit must be at logic 1 to enable the LVI module, and
the LVIRST bit must be at logic 0 to disable LVI resets.
In applications that require V
enabling LVI resets allows the LVI module to reset the MCU when V
falls to the LVI
more consecutive CPU cycles. In the configuration register, the LVIPWR
and LVIRST bits must be at logic 1 to enable the LVI module and to
enable LVI resets.
Freescale Semiconductor, Inc.
Figure 15-2. LVI I/O Register Summary
For More Information On This Product,
Reset:
Read: LVIOUT
Write:
Low-Voltage Inhibit (LVI) Module
Bit 7
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0
TRIPF
= Unimplemented
level and remains at or below that level for nine or
TRIPR
6
0
0
DD
by polling the LVIOUT bit. In the configuration
. V
DD
5
0
0
DD
to remain above the LVI
must be above LVI
DD
4
0
0
levels below the LVI
Low-Voltage Inhibit (LVI) Module
3
0
0
15.4.2 Forced Reset
TRIPR
2
0
0
Functional Description
TRIPF
for only one
Technical Data
DD
TRIPF
1
0
0
level,
rises
level,
Bit 0
0
0
DD