MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 351

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.6 BDLC Protocol Handler
MC68HC908AS60 — Rev. 1.0
NOTE:
During arbitration, or even throughout the transmitting message, when
an opposite bit is detected, transmission is stopped immediately unless
it occurs on the 8th bit of a byte. In this case, the BDLC automatically will
append up to two extra logic 1 bits and then stop transmitting. These two
extra bits will be arbitrated normally and thus will not interfere with
another message. The second logic 1 bit will not be sent if the first loses
arbitration. If the BDLC has lost arbitration to another valid message,
then the two extra logic 1s will not corrupt the current message.
However, if the BDLC has lost arbitration due to noise on the bus, then
the two extra logic 1s will ensure that the current message will be
detected and ignored as a noise-corrupted message.
The protocol handler is responsible for framing, arbitration, CRC
generation/checking, and error detection. The protocol handler
conforms to SAE J1850 Class B Data Communications Network
Interface.
Motorola assumes that the reader is familiar with the J1850 specification
before reading this protocol handler description.
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
Go to: www.freescale.com
Figure 21-13. BDLC Block Diagram
PHYSICAL INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
CPU INTERFACE
TO J1850 BUS
TO CPU
Byte Data Link Controller-Digital (BDLC-D)
BDLC
BDLC Protocol Handler
Technical Data