MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 339
MC68HC908AS60CFN
Manufacturer Part Number
MC68HC908AS60CFN
Description
IC MCU 60K FLASH 8MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908AS60CFN.pdf
(454 pages)
Specifications of MC68HC908AS60CFN
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Quantity
Price
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21.5.2.4 End-of-Data Symbol (EOD)
21.5.2.5 In-Frame Response Bytes (IFR)
MC68HC908AS60 — Rev. 1.0
WARNING:
NOTE:
X
the calculated CRC does not equal $C4, the BDLC will recognize this as
a CRC error and set the CRC error flag in the BSVR.
The EOD symbol is a long 200- s passive period on the J1850 bus used
to signify to any recipients of a message that the transmission by the
originator has completed. No flag is set upon reception of the EOD
symbol.
The IFR section of the J1850 message format is optional. Users desiring
further definition of in-frame response should review the SAE J1850
Class B Data Communications Network Interface specification.
When the BDLC is programmed to transmit a single byte Type 2 IFR
(byte loaded in the BDR and TSIFR bit set in BCR2), the BDLC will
attempt to transmit a single IFR byte following the EOD of the
message currently being received. If the byte to be transmitted
loses arbitration, the BDLC will continue to retry transmission until
it is successful or an error occurs or the TEOD bit is set. When the
BDLC does win arbitration and transmits its single byte IFR, it does
not receive additional IFR bytes transmitted from other nodes
properly, instead generates an invalid symbol interrupt.
The user can compensate for the condition described in the preivous
paragraph by following this procedure:
7
•
•
•
Freescale Semiconductor, Inc.
+ X
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
When the first RXIFR interrupt occurs, the requester message has
been received without errors (invalid symbol or CRC).
When the BDLC receives back correctly the IFR byte it was trying
to transmit, then response by this node is complete. The requester
message received can be passed to the application layer.
Ignore any invalid symbol error that occurs after the first RXIFR
interrupt, since transmission of IFRs are not retried.
6
+ X
2
Go to: www.freescale.com
= $C4, regardless of the data contained in the message. If
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
Technical Data
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