MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 217
MC68HC908AS60CFN
Manufacturer Part Number
MC68HC908AS60CFN
Description
IC MCU 60K FLASH 8MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908AS60CFN.pdf
(454 pages)
Specifications of MC68HC908AS60CFN
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
40
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908AS60CFN
Manufacturer:
MOT
Quantity:
5 510
Company:
Part Number:
MC68HC908AS60CFN
Manufacturer:
TI
Quantity:
5 510
Part Number:
MC68HC908AS60CFN
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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MC68HC908AS60 — Rev. 1.0
$001A
Addr.
IRQ Status and Control
NOTE:
Register (ISCR)
Register Name
See page 220.
The external interrupt pin is falling-edge triggered and is software-
configurable to be both falling-edge and low-level triggered. The MODE1
bit in the ISCR controls the triggering sensitivity of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE1 control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See
•
•
Freescale Semiconductor, Inc.
Figure 16-2. IRQ I/O Register Summary
For More Information On This Product,
Figure
Reset:
Read:
Write:
Vector fetch or software clear
Return of the interrupt pin to logic 1
External Interrupt Module (IRQ)
Bit 7
Go to: www.freescale.com
16-3.)
R
R
0
0
= Reserved
R
6
0
0
R
5
0
0
R
4
0
0
IRQF1
R
3
0
External Interrupt Module (IRQ)
ACK1
2
0
0
Functional Description
IMASK1
Technical Data
1
0
MODE1
Bit 0
0
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