MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 338

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Controller-Digital (BDLC-D)
21.5.2.2 In-Message Data Bytes (Data)
21.5.2.3 Cyclical Redundancy Check Byte (CRC)
Technical Data
IDLE
SOF
PRIORITY
(DATA0)
Figure 21-6. J1850 Bus Message Format (VPW)
DATA
The data bytes contained in the message include the message
priority/type, message ID byte (typically the physical address of the
responder), and any actual data being transmitted to the receiving node.
The message format used by the BDLC is similar to the 3-byte
consolidated header message format outlined by the SAE J1850
document. See SAE J1850 Class B Data Communications Network
Interface for more information about 1- and 3-byte headers.
Messages transmitted by the BDLC onto the J1850 bus must contain at
least one data byte, and, therefore, can be as short as one data byte and
one CRC byte. Each data byte in the message is eight bits in length and
is transmitted MSB to LSB (least significant bit).
This byte is used by the receiver(s) of each message to determine if any
errors have occurred during the transmission of the message. The BDLC
calculates the CRC byte and appends it onto any messages transmitted
onto the J1850 bus. It also performs CRC detection on any messages it
receives from the J1850 bus.
CRC generation uses the divisor polynomial X
remainder polynomial initially is set to all 1s. Each byte in the message
after the start-of-frame (SOF) symbol is processed serially through the
CRC generation circuitry. The one’s complement of the remainder then
becomes the 8-bit CRC byte, which is appended to the message after
the data bytes, in MSB-to-LSB order.
When receiving a message, the BDLC uses the same divisor
polynomial. All data bytes, excluding the SOF and end of data symbols
(EOD) but including the CRC byte, are used to check the CRC.
If the message is error free, the remainder polynomial will equal
Freescale Semiconductor, Inc.
MESSAGE ID
(DATA1)
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
Go to: www.freescale.com
DATA
N
CRC
E
O
D
N
B
OPTIONAL
8
MC68HC908AS60 — Rev. 1.0
IFR
+ X
4
+ X
3
EOF
+ X
2
S
F
+ 1. The
I
IDLE