MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 316

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Input/Output (I/O) Ports
20.7.2 Data Direction Register E
Technical Data
NOTE:
NOTE:
Address:
TxD — SCI Transmit Data Output
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See
Data direction register E (DDRE) determines whether each port E pin is
an input or an output. Writing a logic 1 to a DDRE bit enables the output
buffer for the corresponding port E pin; a logic 0 disables the output
buffer.
DDRE[7:0] — Data Direction Register E Bits
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 20-16
Reset:
Read:
Write:
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. (See
17.9.1 SCI Control Register
These read/write bits control port E data direction. Reset clears
DDRE[7:0], configuring all port E pins as inputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
DDRE7
$000C
Bit 7
Figure 20-15. Data Direction Register E (DDRE)
0
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shows the port E I/O logic.
Input/Output (I/O) Ports
DDRE6
6
0
DDRE5
5
0
DDRE4
1.)
4
0
Table
DDRE3
3
0
20-5.)
MC68HC908AS60 — Rev. 1.0
DDRE2
2
0
DDRE1
1
0
DDRE0
Bit 0
0