MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 281

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

18.13.4 SS (Slave Select)
MC68HC908AS60 — Rev. 1.0
NOTE:
The SS pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS is used to select a slave.
For CPHA = 0, the SS is used to define the start of a transmission. (See
18.6 Transmission
transmission, the SS must be toggled high and low between each byte
transmitted for the CPHA = 0 format. However, it can remain low
throughout the transmission for the CPHA = 1 format. See
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See
18.14.2 SPI Status and Control
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK
clocks, even if a transmission already has begun.
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See
SS pin to set the MODF flag, the MODFEN bit in the SPSCK register
must be set. If the MODFEN bit is low for an SPI master, the SS pin can
be used as a general-purpose I/O under the control of the data direction
register of the shared I/O port. With MODFEN high, it is an input-only pin
to the SPI regardless of the state of the data direction register of the
shared I/O port.
MASTER SS
MISO/MOSI
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
Figure 18-11. CPHA/SS Timing
BYTE 1
Formats.) Since it is used to indicate the start of a
18.7.2 Mode Fault
Register.)
BYTE 2
Error.) For the state of the
Serial Peripheral Interface (SPI)
BYTE 3
Figure
Technical Data
I/O Signals
18-11.