MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 336

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Controller-Digital (BDLC-D)
21.5.1.1 Operation
21.5.1.2 Performance
Technical Data
The clock for the digital filter is provided by the MUX interface clock (see
f
signal, the current state of the receiver physical interface (BDRxD) signal
is sampled. The BDRxD signal state is used to determine whether the
counter should increment or decrement at the next negative edge of the
clock signal.
The counter will increment if the input data sample is high but decrement
if the input sample is low. Therefore, the counter will thus progress either
up toward 15 if, on average, the BDRxD signal remains high or progress
down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter
decides that the condition of the BDRxD signal is at a stable logic level
1 and the data latch is set, causing the filtered Rx data signal to become
a logic level 1. Furthermore, the counter is prevented from overflowing
and can be decremented only from this state.
Alternatively, should the counter eventually reach the value 0, the digital
filter decides that the condition of the BDRxD signal is at a stable logic
level 0 and the data latch is reset, causing the filtered Rx data signal to
become a logic level 0. Furthermore, the counter is prevented from
underflowing and can only be incremented from this state.
The data latch will retain its value until the counter next reaches the
opposite end point, signifying a definite transition of the signal.
The performance of the digital filter is best described in the time domain
rather than the frequency domain.
If the signal on the BDRxD signal transitions, then there will be a delay
before that transition appears at the filtered Rx data output signal. This
delay will be between 15 and 16 clock periods, depending on where the
transition occurs with respect to the sampling points. This filter delay
must be taken into account when performing message arbitration.
BDLC
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Table
21-3). At each positive edge of the clock
MC68HC908AS60 — Rev. 1.0