MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 356

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Controller-Digital (BDLC-D)
21.6.5.5 Summary
Technical Data
BREAK — Break
Transmission error
Cyclical redundancy
Invalid symbol: BDLC transmits,
Framing error
Bus short to V
Bus short to GND
BDLC receives BREAK symbol
check (CRC) error
but receives invalid bits (noise)
In any case, if the bus fault is temporary, as soon as the fault is
cleared, the BDLC will resume normal operation. If the bus fault is
permanent, it may result in permanent loss of communication on the
J1850 bus. (See
If a BREAK symbol is received while the BDLC is transmitting or
receiving, an invalid symbol (in BSVR) interrupt will be generated.
Reading the BSVR (see
clear this interrupt condition. The BDLC will wait for the bus to idle,
then wait for a start-of-frame (SOF) symbol.
The BDLC cannot transmit a BREAK symbol. It only can receive a
BREAK symbol from the J1850 bus.
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
Error Condition
Table 21-1. BDLC J1850 Bus Error Summary
DD
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21.7.4 BDLC State Vector
21.7.4 BDLC State Vector
For invalid bits or framing symbols on non-byte
CRC error interrupt will be generated. The
The BDLC will abort transmission immediately.
Invalid symbol interrupt will be generated.
The BDLC will not transmit until the bus is idle.
Thermal overload will shut down physical
Invalid symbol interrupt will be generated. The
boundaries, invalid symbol interrupt will be
generated. BDLC stops transmission.
BDLC will wait for EOF.
Invalid symbol interrupt will be generated.
The BDLC will wait for end of frame (EOF).
Invalid symbol interrupt will be generated.
EOF interrupt also must be seen before
another transmission attempt. Depending on
length of the short, LOA flag also may be set.
interface. Fault condition is seen as invalid
symbol flag. EOF interrupt must also be seen
before another transmission attempt.
BDLC will wait for the next valid SOF.
BDLC Function
MC68HC908AS60 — Rev. 1.0
Register.)
Register) will