MC68HC908AS60CFN Freescale Semiconductor, MC68HC908AS60CFN Datasheet - Page 354

• Manufacturer Part Number: MC68HC908AS60CFN
• Description: IC MCU 60K FLASH 8MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AS60CFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Controller-Digital (BDLC-D)
21.6.5.2 Receiving a Message in Block Mode
21.6.5.3 Transmitting a Message in Block Mode
21.6.5.4 J1850 Bus Errors
Technical Data
RX4XE bit is not set in the BCR2, any 4X message on the J1850 bus is
treated as noise by the BDLC and is ignored.
Although not a part of the SAE J1850 protocol, the BDLC does allow for
a special block mode of operation of the receiver. As far as the BDLC is
concerned, a block mode message is simply a long J1850 frame that
contains an indefinite number of data bytes. All other features of the
frame remain the same, including the SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first
inform all other nodes on the network that this is about to happen. This
is usually accomplished by sending a special predefined message.
A block mode message is transmitted inherently by simply loading the
bytes one by one into the BDR until the message is complete. The
programmer should wait until the TDRE flag (see
Vector
The BDLC does not contain any predefined maximum J1850 message
length requirement.
The BDLC detects several types of transmit and receive errors which
can occur during the transmission of a message onto the J1850 bus.
Transmission Error
If the message transmitted by the BDLC contains invalid bits or
framing symbols on non-byte boundaries, this constitutes a
transmission error. When a transmission error is detected, the BDLC
immediately will cease transmitting. The error condition is reflected in
the BSVR (see
set, a CPU interrupt request from the BDLC is generated.
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
Register) is set prior to writing a new byte of data into the BDR.
Go to: www.freescale.com
Table
21-5). If the interrupt enable bit (IE in BCR1) is
MC68HC908AS60 — Rev. 1.0
21.7.4 BDLC State