MC68HC908EY16CFA Freescale Semiconductor, MC68HC908EY16CFA Datasheet - Page 119

• Manufacturer Part Number: MC68HC908EY16CFA
• Description: IC MCU 16K FLASH 8MHZ SPI 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908EY16CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: POR, PWM
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: HC08EY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08EY-A
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

12.4 Port C
Port C is an 5-bit general-purpose bidirectional I/O port that shares pin functions with the internal clock
generator (ICG) and serial peripheral interface (SPI) modules.
12.4.1 Port C Data Register
The port C data register contains a data latch for each of the five port C pins.
PTC[4:0] — Port C Data Bits
MCLK — T12 System Clock Bit
12.4.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input or an output. Writing a 1 to a
DDRC bit enables the output buffer for the corresponding port C pin; a 0 disables the output buffer.
MCLKEN — MCLK Enable Bit
Freescale Semiconductor
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data.
The system clock is driven out of PTC2 when enabled by MCLKEN bit in PTCDDR7.
This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, PTC2 is under
the control of MCLKEN. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
Alternative Function:
Address:
Reset:
Read:
Write:
Address:
Reset:
Read:
Write:
MCLKEN
$0006
Bit 7
0
$0002
Figure 12-8. Data Direction Register C (DDRC)
Bit 7
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
0
= Unimplemented
Figure 12-7. Port C Data Register (PTC)
6
0
0
= Unimplemented
6
0
5
0
0
5
0
DDRC4
4
0
Unaffected by reset
OSC1
PTC4
4
DDRC3
3
0
OSC2
PTC3
3
DDRC2
2
0
MCLK
PTC2
2
DDRC1
1
0
PTC1
MOSI
1
DDRC0
Bit 0
0
PTC0
MISO
Bit 0
Port C
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