MC68HC908EY16CFA Freescale Semiconductor, MC68HC908EY16CFA Datasheet - Page 91

• Manufacturer Part Number: MC68HC908EY16CFA
• Description: IC MCU 16K FLASH 8MHZ SPI 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908EY16CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: POR, PWM
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: HC08EY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08EY-A
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

8.4.4.2 Binary Weighted Divider
The binary weighted divider divides the output of the ring oscillator by a power of two, specified by the
DCO divider control bits (DDIV[3:0]). DDIV maximizes at %1001 (values of %1010 through %1111 are
interpreted as %1001), which corresponds to a divide by 512. When DDIV is %0000, the ring oscillator’s
output is divided by 1. Incrementing DDIV by one will double the period; decrementing DDIV will halve the
period. The DLF cannot directly increment or decrement DDIV; DDIV is only incremented or decremented
when an addition or subtraction to DSTG carries or borrows.
8.4.4.3 Variable-Delay Ring Oscillator
The variable-delay ring oscillator’s period is adjustable from 17 to 31 stage delays, in increments of two,
based on the upper three DCO stage control bits (DSTG[7:5]). A DSTG[7:5] of %000 corresponds to 17
stage delays; DSTG[7:5] of %111 corresponds to 31 stage delays. Adjusting the DSTG[5] bit has a 6.45
percent to 11.8 percent effect on the output frequency. This also corresponds to the size correction made
when the frequency error is greater than ±15 percent. The value of the binary weighted divider does not
affect the relative change in output clock period for a given change in DSTG[7:5].
8.4.4.4 Ring Oscillator Fine-Adjust Circuit
The ring oscillator fine-adjust circuit causes the ring oscillator to effectively operate at non-integer
numbers of stage delays by operating at two different points for a variable number of cycles specified by
the lower five DCO stage control bits (DSTG[4:0]). For example:
Freescale Semiconductor
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•
•
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When DSTG[7:5] is %011, the ring oscillator nominally operates at 23 stage delays.
When DSTG[4:0] is %00000, the ring will always operate at 23 stage delays.
When DSTG[4:0] is %00001, the ring will operate at 25 stage delays for one of 32 cycles and at 23
stage delays for 31 of 32 cycles.
Likewise, when DSTG[4:0] is %11111, the ring operates at 25 stage delays for 31 of 32 cycles and
at 23 stage delays for one of 32 cycles.
%0101–%1001 (max)
%0000 (min)
%0000 (min)
%0000 (min)
DDIV[3:0]
%0001
%0001
%0001
%0010
%0010
%0010
%0011
%0011
%0100
%0100
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Table 8-2. Quantization Error in ICLK
ICLK Cycles
≥ 32
≥ 16
≥ 8
≥ 4
≥ 2
≥ 1
1
4
1
4
1
4
1
1
Bus Cycles
NA
≥ 8
NA
≥ 4
NA
≥ 2
NA
≥ 1
NA
≥ 1
≥ 1
1
1
1
0.202%–0.368%
0.202%–0.368%
0.403%–0.735%
0.202%–0.368%
0.202%–0.368%
0.403%–0.735%
0.202%–0.368%
0.202%–0.368%
0.806%–1.47%
0.806%–1.47%
6.45%–11.8%
1.61%–2.94%
3.23%–5.88%
1.61%–2.94%
τ
ICLK
Q-ERR
Usage Notes
91