HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 130

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.6
6.6.1
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent,
3. The interrupt controller compares the priority level of the selected interrupt request with the
4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin.
5. The CPU detects the interrupt request sent from the interrupt controller when CPU decodes the
6. SR and PC are saved onto the stack.
7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in
8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high
9. The CPU reads the start address of the exception service routine from the exception vector
Note: * Interrupt requests that are designated as edge-detect type are held pending until the
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according to the priority levels set in interrupt priority level setting registers A, D to I, K
(IPRA, IPRD to IPRI, IPRK). Interrupts that have lower-priority than that of the selected
interrupt are ignored.* If interrupts that have the same priority level or interrupts within a same
module occur simultaneously, the interrupt with the highest priority is selected according to the
default priority order indicated in table 6.2.
interrupt mask bits (I3 to I0) in the CPU’s status register (SR). If the request priority level is
equal to or less than the level set in I3 to I0, the request is ignored. If the request priority level
is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception processing (figure 6.5).
the status register (SR).
level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high
level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception
processing instead of instruction execution as noted in (5) above. However, if the interrupt
controller accepts an interrupt with a higher priority than the interrupt just to be accepting, the
IRQOUT pin holds low level.
table for the accepted interrupt, jumps to that address, and starts executing the program. This
jump is not a delay branch.
Interrupt Operation
Interrupt Sequence
interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing
the IRQ status register (ISR). Interrupts held pending due to edge detection are cleared
by a power-on reset or a manual reset.