HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 497

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.3.18 Timer Control Register (TCR)
TCR is a 16-bit readable/writable register that controls the timer operation. This register performs
all the settings of periodic transmit condition and restriction. This register should be set before
starting timer operation.
Bit
15
14
13
Bit Name
TCR15
TCR14
TCR13
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Enable Timer
Controls on/off of the timer.
0: Timer stops running
1: Timer starts running
Notes: 1. The timer does not stop running immediately
Disable ICR0
Controls whether to enable or disable the input capture
register 0 (ICR0). When this bit is set to 1, the timer
value is always captured every time a StartOfFrame
(SOF) appears on the CAN bus, regardless of whether
the HCAN2 is a transmitter or receiver. When this bit is
cleared to 0, the ICR0 value remains latched.
0: ICR0 is disabled
1: ICR0 is enabled and captures the timer value at every
[Clearing condition]
•
Timestamp Control for Reception
Specifies if the timestamp of each mailbox is recorded at
the start of frame (SOF) or end of frame (EOF). Selects
ICR1 which becomes a trigger of the timestamp for
operation in reception.
0: Timestamp is recorded at every SOF
1: Timestamp is recorded at every EOF
Note:
SOF
CAN-ID of the receive message = mailbox with CCM
set (when TCR9 = 1)
2. The timer malfunctions in this LSI. To
In this LSI, timestamp is not recorded at every
SOF. When using the timestamp in reception,
write 1 to this bit.
after this bit is cleared to 0. The timer stops
running after an overflow or compare match
occurred.
prevent the timer from running, the write
value to this bit should always be 0.
Rev. 2.00, 09/04, page 455 of 720