HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 49

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Type
Operating
mode control
System
control
Interrupts
Address bus A17 to A0
Data bus
Symbol
MD3
MD2
MD1
MD0
FWP
RES
MRES
HSTBY
WDTOVF
BREQ
BACK
NMI
IRQ3
IRQ2
IRQ1
IRQ0
IRQOUT
D7 to D0
Input
Input
I/O
Input
Input
Input
Input
Output
Input
Output
Input
Output
Output
Input/
Output
Name
Set the mode
Protection
against write
operation into
Flash memory
Power on
reset
Manual reset
Standby
Watchdog
timer overflow
Bus request
Bus
acknowledge
Non-maskable
interrupt
Interrupt
request 3 to 0
Interrupt
request output
Address bus
Data bus
Set the operating mode. Inputs at these
When this pin is driven low, a transition is
Function
pins should not be changed during
operation.
Pin for the flash memory. This pin is only
used in the flash memory version. Writing
or erasing of flash memory can be
protected. This pin becomes the Vcc pin
for the mask ROM version.
When this pin is driven low, the chip
becomes to power on reset state.
When this pin is driven low, the chip
becomes to manual reset state.
made to hardware standby mode.
Output signal for the watchdog timer
overflow. If this pin need to be pulled-
down, use the resistor larger than 1 MΩ to
pull the pin down.
External device can request the release of
the bus mastership by setting this pin low.
Shows that the bus mastership has been
released for the external device. The
device that had issued the BREQ signal
can know that bus mastership has been
released for itself by receiving the BACK
signal.
Non-maskable interrupt pin. If this pin is
not used, it should be fixed high, or fixed
low.
These pins request a maskable interrupt.
One of the level input or edge input can
be selected. In case of the edge input,
one of the rising edge, falling edge, or
both can be selected.
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release state.
Output the address.
Bi-directional 8-bits bus.
Rev. 2.00, 09/04, page 7 of 720