HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 513
![IC SUPERH MCU FLASH 256K 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
HD64F7047F50
Manufacturer Part Number
HD64F7047F50
Description
IC SUPERH MCU FLASH 256K 100QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047F50
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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• Remote frame reception
Unread Message Overwrite: If the receive message identifier matches the mailbox identifier, the
receive message is stored in the mailbox regardless of whether the mailbox contains an unread
message or not. If a message overwrite occurs, the corresponding bit (UMSR0 to UMSR31) is set
in the unread message register (UMSR). In overwriting an unread message, when a new message
is received before the corresponding bit in the receive complete register (RXPR) has been cleared,
the unread message register (UMSR) is set. If the unread interrupt flag (IRR9) in the interrupt
mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the
CPU. Figure 15.11 shows a flowchart for unread message overwriting.
Two kinds of messages—data frames and remote frames—can be stored in mailboxes. A
remote frame differs from a data frame in that the value of the remote transmission request bit
(RTR) in the message control and the data field are 0 bytes long. The data length to be returned
in a data frame must be stored in the data length code (DLC) in the control field.
When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote
request wait register (RFPR). If the corresponding bit (MBIMR0 to MBIMR31) in the mailbox
interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the
interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt
request (RM1) can be sent to the CPU.
Message control/message data read
Figure 15.11 Unread Message Overwrite Flowchart
Unread message overwrite
Interrupt to CPU (OVR1)
Clear IRR9
UMSR = 1
IMR9 = 1?
IRR9 = 1
End
No
Yes
: Settings by user
: Processing by hardware
Rev. 2.00, 09/04, page 471 of 720
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