HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 427

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit
7
6
5
4
3
2 to 0 
Bit Name
TRGE
CKS1
CKS0
ADST
ADCS
Initial
Value
0
0
0
0
0
All 1
R/W
R/W
R/W
R/W
R/W
R/W
R
Trigger Enable
Description
Enables or disables triggering of A/D conversion by
ADTRG, an MTU trigger, or an MMT trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
Clock Select 0 and 1
Select the A/D conversion time.
00: Pφ/32
01: Pφ/16
10: Pφ/8
11: Pφ/4
When changing the A/D conversion time, first clear the
ADST bit in the A/D control registers (ADCRs) to 0.
CKS[1,0] = b'11 can be set while Pφ ≤ 25 MHz.
A/D Start
Starts or stops A/D conversion. When this bit is set to 1,
A/D conversion is started. When this bit is cleared to 0,
A/D conversion is stopped and the A/D converter enters
the idle state. In single or single-cycle scan mode, this bit
is automatically cleared to 0 when A/D conversion ends on
the selected single channel. In continuous scan mode, A/D
conversion is continuously performed for the selected
channels in sequence until this bit is cleared by a software,
reset, or in software standby mode, hardware standby
mode, or module standby mode.
A/D Continuous Scan
Selects either single-cycle scan or continuous scan in
scan mode. This bit is valid only when scan mode is
selected.
0: Single-cycle scan
1: Continuous scan
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
Reserved
These bits are always read as 1, and should only be
written with 1.
Rev. 2.00, 09/04, page 385 of 720