HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 411

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.6.3
Figure 12.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
written to TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty (TXI)
interrupt request is generated. Because the TXI interrupt routine writes the next transmit data
to TDR before transmission of the current transmit data has finished, continuous transmission
can be enabled.
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be
Set CKE1 and CKE0 bits in SCR
Set PFC of the external pin used
Set TE and RE bits in SCR to 1
Serial data transmission (Clocked Synchronous mode)
Clear RIE, TIE, TEIE, MPIE,
TE and RE bits in SCR to 0*
Set RIE, TIE, and TEIE bits
Set data transfer format in
(TE and RE bits are 0)
1-bit interval elapsed?
cleared to 0 or set to 1 simultaneously.
Start initialization
Set value in BRR
<Transfer start>
SCK, TxD, RxD
SMR
Figure 12.15 Sample SCI Initialization Flowchart
Yes
Wait
No
[4]
[5]
[2]
[3]
[1]
[1] Set the clock selection in SCR.
[2] Set the data transfer format in SMR.
[3] Write a value corresponding to the bit
[4] Set PFC of the external pin used. Set
[5] Wait at least one bit interval, then set
rate to BRR. Not necessary if an
external clock is used.
RxD input during receiving and TxD
output during transmitting. Set SCK
input/output according to contents set
by CKE1 and CKE0.
the TE bit or RE bit in SCR to 1.* At this
time, the TxD, RxD, and SCK pins can
be used. The TxD pin is in a mark state
during transmitting. When synchronous
clock output (clock master) is set during
receiving in synchronous mode,
outputting clocks from the SCK pin
starts.
Rev. 2.00, 09/04, page 369 of 720