ST16C554DIJ68-F Exar Corporation, ST16C554DIJ68-F Datasheet - Page 11

• Manufacturer Part Number: ST16C554DIJ68-F
• Description: IC UART FIFO 16B QUAD 68PLCC
• Manufacturer: Exar Corporation
• Type: Quad UART with 16-byte FIFOsr

Specifications of ST16C554DIJ68-F

• Number Of Channels: 4, QUART
• Package / Case: 68-LCC (J-Lead)
• Features: *
• Fifo's: 16 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• No. Of Channels: 4
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1267-5

REV. 4.0.1
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
sampling clock. A bit time is 16X clock periods. The transmitter sends the start-bit followed by the number of
data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are
reported in the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
F
O
2.9
2.9.1
IGURE
UTPUT
MCR Bit-7=1
115.2k
230.4k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
5. B
Data Rate
Transmitter
Transmit Holding Register (THR) - Write Only
AUD
T
ABLE
R
ATE
XTAL1
XTAL2
O
UTPUT
6: T
MCR Bit-7=0
(D
G
153.6k
230.4k
460.8k
921.6k
ENERATOR
EFAULT
19.2k
38.4k
76.8k
YPICAL DATA RATES WITH A
2400
4800
9600
400
Data Rate
Crystal
Buffer
Osc /
)
Clock (Decimal)
D
IVISOR FOR
To Other
Channels
2304
384
192
96
48
24
12
6
4
2
1
16x
14.7456 MH
D
Rate Generator Logic
11
Programmable Baud
IVISOR FOR
Clock (HEX)
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
900
180
C0
0C
60
30
18
06
04
02
01
DLL and DLM
Registers
Z CRYSTAL OR EXTERNAL CLOCK
16x
V
ALUE
P
ROGRAM
DLM
16 X Sampling
09
01
00
00
00
00
00
00
00
00
00
and Receiver
to Transmitter
(HEX)
Rate Clock
V
ALUE
P
ROGRAM
ST16C554/554D
DLL
C0
0C
00
80
60
30
18
06
04
02
01
(HEX)
D
E
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)